Record-Breaking Carbon Nanotube Transistors: A Milestone by Professor Peng Lian-Mao’s Team

As traditional silicon-based transistors approach physical limits—especially at sub-5nm nodes—new challenges like increased leakage current and short-channel effects hinder further performance improvement. This has spurred the search for alternative materials and innovative architectures. Aligned Carbon Nanotubes (A-CNTs) have emerged as a promising solution, offering atomic-level thickness, high carrier mobility, and superior electrostatic gate control, making them ideal candidates for future transistor technology.

Key Achievements with Dual-Gate Architecture

In this study, Professor Peng Lian-Mao’s team from Peking University highlights the advantages of using a dual-gate (DG) architecture to enhance the performance of A-CNT-based transistors. Compared to traditional single-gate field-effect transistors (SG-FETs), dual-gate devices provide better channel control, mitigating many issues encountered by short-channel devices. Through optimized gate materials and dielectric configurations, the dual-gate structure significantly improves switching characteristics and boosts overall performance.

Material Selection and Configuration Breakthroughs

One critical challenge faced during the research was identifying the optimal gate metal and dielectric materials. Differences in the work functions of the top and bottom gate metals could degrade transistor performance. After extensive testing, palladium (Pd) was identified as the ideal gate metal, providing stable performance and appropriate work functions for both gates. Additionally, the 4nm-thick hafnium oxide (HfO₂) dielectric layer minimized leakage current and maximized gate control, further enhancing device performance.

Record-Breaking Performance Metrics

The study demonstrated several key improvements:

• On-current density (Ion): 1.47 mA/μm
• Peak transconductance (Gm): 2 mS/μm
• Subthreshold slope (SS): 83 mV/decade, approaching theoretical limits
• On/Off ratio: 10⁶, indicating excellent switching behavior

These results surpass prior reports on CNT-based transistors, showcasing the potential of A-CNT dual-gate FETs (DG-FETs) for high-performance, low-power integrated circuits.

The Impact of Gate Materials and Dielectrics

The study also explored different gate metals—including platinum (Pt), Pd, gold (Au), titanium (Ti), and aluminum (Al)—to determine the most effective top-gate material. Metals with higher work functions, such as Pt and Pd, exhibited superior switching characteristics, while those with lower work functions, like Ti and Al, performed poorly. Reducing the dielectric thickness from 20nm to 4nm minimized hysteresis (as low as 10mV) and improved switching speed, further boosting efficiency.

Simulation and Theoretical Insights

Using TCAD simulations, the team explored the impact of work function differences between the top and bottom gates. These simulations confirmed that minimizing these differences maximizes gate efficiency, leading to enhanced transistor performance. The theoretical analysis validated the experimental results, emphasizing the importance of material selection in optimizing dual-gate FET performance.

Future Potential and Challenges

Compared with traditional silicon transistors and other CNT designs, the A-CNT DG-FETs exhibited exceptional performance, particularly in current density, transconductance, and power efficiency. These attributes position them as strong candidates for sub-1nm node devices, capable of surpassing silicon in speed, power efficiency, and scalability.

However, challenges remain, particularly in the development of complementary n-type CNT transistors. Most current research focuses on p-type A-CNT transistors, but n-type devices with comparable characteristics are essential for practical logic circuits. Scaling up these experimental results to industrial processes will also require advancements in CNT alignment and material purity.

Outlook for Next-Generation Electronics

The optimized DG-FET design holds significant promise for sub-1nm integrated circuits, providing a viable pathway for continuing the miniaturization of electronic devices beyond the limits of silicon technology. These breakthroughs pave the way for further exploration and practical applications of CNT-based transistors in high-performance electronics.

With record-setting transistor performance, this research demonstrates that A-CNT DG-FETs could become a viable alternative to traditional technologies, laying the groundwork for future studies and integration with commercial semiconductor processes.

Original Source: DOI: 10.1021/acsami.4c12453